/////////////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ns
`define CLK_PERIOD 20

module ad9226_sdram_uart_tb();

	reg clk;
	reg reset_n;
	
	reg uart_send_en;
	reg [7:0] uart_tx_data;
	
	wire uart_tx_done;
  
  	wire	sdram_clk;
	wire	sdram_cke;
	wire	sdram_cs_n;
	wire	sdram_we_n;
	wire	sdram_cas_n;
	wire	sdram_ras_n;
	wire	[1:0]sdram_dqm;
	wire	[1:0]sdram_ba;
	wire	[12:0]sdram_addr;
	wire	[15:0]sdram_dq;
	

	wire	[1:0] led;
	wire	uart_tx_cmd;
	wire	uart_tx;
	wire	[11:0]ad_in1;
	wire	[11:0]ad_in2;
	wire	ad_clk1;
	wire	ad_clk2;
	wire	uart_rx;

	initial clk= 1;
	always#(`CLK_PERIOD/2) clk = ~clk;

AC620_AD9226_sdram_uart AC620_AD9226_sdram_uart_0(
	.clk(clk),
	.reset_n(reset_n),
	//LED
	.led(led),

	//ADC
	.ad_in1(ad_in1),
	.ad_in2(ad_in2),
	.ad_clk1(ad_clk1),
	.ad_clk2(ad_clk2),
	
	.uart_rx(uart_rx),
	
	//sdram control
	.sdram_clk(sdram_clk),
	.sdram_cke(sdram_cke),
	.sdram_cs_n(sdram_cs_n),
	.sdram_we_n(sdram_we_n),
	.sdram_cas_n(sdram_cas_n),
	.sdram_ras_n(sdram_ras_n),
	.sdram_dqm(sdram_dqm),
	.sdram_ba(sdram_ba),
	.sdram_addr(sdram_addr),
	.sdram_dq(sdram_dq),
	
	.uart_tx(uart_tx)
);
//wait	(uart_cmd_rx_1.adc_ch_sel == 1)

	reg cnt_req;
	reg [56:0]ad_cnt;
	always@(posedge clk or negedge reset_n)
	if(!reset_n)
	ad_cnt <= 16'd0;
	else if(cnt_req == 1'b1)begin
		if(ad_cnt == 56'd99999999999999)
			ad_cnt <= 16'd0;
		else 
			ad_cnt <= ad_cnt + 1'b1;
	end
	else
		ad_cnt <= 16'd0;
	 
	assign	ad_in1 = ad_cnt;
	assign	ad_in2 = ad_cnt;
	  
	initial begin
	  cnt_req = 1'b0;
	  @(posedge AC620_AD9226_sdram_uart_0.ad_sample_en)
	  cnt_req = 1'b1;
	  #100;
	  wait(AC620_AD9226_sdram_uart_0.ad_sample_en == 0);
		cnt_req = 1'b0;  

	end


initial begin
  reset_n=1'b0;
  #(`CLK_PERIOD*10);
  reset_n=1'b1;
  uart_send_en = 1'b0;
  uart_tx_data = 8'd0;
//  @(posedge AC620_AD9226_sdram_uart_0.uart_tx_done);
  #(`CLK_PERIOD*10+1);
  //启动采集,仿真串口发送55 A5 00 00 00 00 00 F0
  uart_tx_data = 8'h55;
  uart_send_en = 1'b1;//-----发送55
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'hA5;
  uart_send_en = 1'b1;//-----发送A5
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h02;
  uart_send_en = 1'b1;//-----发送00
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h00;
  uart_send_en = 1'b1;//-----发送00
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h00;
  uart_send_en = 1'b1;//-----发送00
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h80;
  uart_send_en = 1'b1;//-----发送80
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h00;
  uart_send_en = 1'b1;//-----发送00
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'hF0;
  uart_send_en = 1'b1;//-----发送F0
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);
  
   //启动采集,仿真串口发送55 A5 00 00 00 00 01 F0
  #(`CLK_PERIOD*10+1);
	 
  uart_tx_data = 8'h55;
  uart_send_en = 1'b1;//-----发送55
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'hA5;
  uart_send_en = 1'b1;//-----发送A5
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h01;
  uart_send_en = 1'b1;//-----发送00
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h00;
  uart_send_en = 1'b1;//-----发送00
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h00;
  uart_send_en = 1'b1;//-----发送00
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h00;
  uart_send_en = 1'b1;//-----发送00
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h01;
  uart_send_en = 1'b1;//-----发送01
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'hF0;
  uart_send_en = 1'b1;//-----发送F0
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);
  
  //启动采集,仿真串口发送55 A5 00 00 00 27 0F F0
  #(`CLK_PERIOD*10+1);
  uart_tx_data = 8'h55;
  uart_send_en = 1'b1;//-----发送55
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'hA5;
  uart_send_en = 1'b1;//-----发送A5
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h00;
  uart_send_en = 1'b1;//-----发送00
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h00;
  uart_send_en = 1'b1;//-----发送00
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h00;
  uart_send_en = 1'b1;//-----发送00
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h27;
  uart_send_en = 1'b1;//-----发送27
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'h0F;
  uart_send_en = 1'b1;//-----发送0F
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);

  #(`CLK_PERIOD*10+1);

  uart_tx_data = 8'hF0;
  uart_send_en = 1'b1;//-----发送F0
  #(`CLK_PERIOD);
  uart_send_en = 1'b0;
  @(posedge uart_tx_done);
  
  #(`CLK_PERIOD*10+1);

  
  repeat(512)
    @(posedge AC620_AD9226_sdram_uart_0.uart_tx_done);

  #2000;
  $stop;
end

	uart_byte_tx uart_byte_tx_cmd(
		.clk (clk),//50M时钟输入,
		.reset_n (reset_n),//模块复位,
		.data_byte (uart_tx_data ),//待传输8bit数据,
		.send_en (uart_send_en ),//发送使能,
		.baud_set (4'd4),//串口波特率设置
		.uart_tx (uart_rx),//Rs232输出信号,
		.tx_done (uart_tx_done),//一次发送数据完成标志,
		.uart_state() //发送数据状态
	);

	//SDRAM模型例化
	sdr sdram_model(
		.Dq(sdram_dq),
		.Addr(sdram_addr),
		.Ba(sdram_ba),
		.Clk(sdram_clk),
		.Cke(sdram_cke),
		.Cs_n(sdram_cs_n),
		.Ras_n(sdram_ras_n),
		.Cas_n(sdram_cas_n),
		.We_n(sdram_we_n),
		.Dqm(sdram_dqm)
	);

endmodule